Drive Circuit, A Display Device Provided With The Same

ABSTRACT

In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

TECHNICAL FIELD

The present invention relates to a drive circuit, in particular to adrive circuit suitable for use in a source driver circuit in an activematrix liquid crystal display (AMLCD).

BACKGROUND ART

FIG. 1 is a schematic view of an active matrix liquid crystal display.As is well-know, an AMLCD comprises a liquid crystal layer in which aplurality of independently addressable pixels P_(ij) are defined, forexample by a patterned electrode. The pixels P_(ij) are generallyarranged in a matrix of rows and columns, as shown in FIG. 1. The pixelmatrix in FIG. 1 has m pixel columns and n pixel rows. Each pixelcontains a portion D_(ij) of the liquid crystal layer of the AMLCD,connected to a switching element T_(ij) which may be, for example, athin film transistor. The gates of all TFTs within a row j of pixels areconnected to a gate line G_(j), and each gate line is connected to agate driver 1. The sources of all TFTs within a column i of pixels areconnected to a source line S_(i), and each source line is connected to asource driver 2. Image data for display is input to the source driver 2,for example over video lines.

In a typical display-driving scheme, the gate driver 1 selects a row ofpixels by driving one gate line G_(j) to be “high” thereby to turn onall the TFTs whose gates are connected to that gate line, and keepingall other gate lines “low”. The source driver 2 samples input imagedata, and outputs corresponding voltages to each of the source lines.The voltage output on a particular source line is coupled to the pixelthat is in the column of pixels connected to that source line and thatis connected to the gate line G_(j) which is being driven “high” by thegate driver.

Once the image data for a row of pixels has been sampled by the sourcedriver and the source driver has output corresponding voltages to eachsource line, the gate driver selects the next row of pixels by drivinganother gate line, usually the next gate line G_(j+1), “high” andkeeping all other gate lines “low”, and the above process is repeated.Usually, an image is displayed by selecting pixels from left to rightand from top to bottom.

Each pixel P_(ij) may comprise a capacitor C_(ij) connected in parallelwith the liquid crystal element D_(ij), for stabilising the voltagemaintained across the liquid crystal element D_(ij) while the TFT T_(ij)is off between two successive operations of addressing that pixel.

In a full colour AMLCD, each pixel within the pixel matrix may typicallyconsist of a red segment, a green segment and a blue segment. Eachsegment corresponds generally to the pixel P_(ij) shown in FIG. 1, andeach segment contains a TFT to control the voltage applied across thepart of the liquid crystal layer in that segment. Thus, in a full-colourAMLCD there are three source lines for each one column of pixels.

A typical source driver is shown in FIG. 2. The source driver 2 containsa shift register 3, a level shifter 4 comprising a plurality of levelshifter circuits 4 _(i) (where i=0, 1, 2 . . . (m−1)), and a sampler 5comprising a plurality of sampling circuits 5 _(i) (where i=0, 1, 2 . .. (m−1)). The shift register 3 is connected to first and second voltagesupply lines 7, 8 which provide first and second supply voltages V_(DD),V_(SS) respectively. The sampler 5 has input data lines 9 for receivingan input data signal that defines a image to be displayed on the AMLCD;the input data lines 9 may be video lines and the input data signal maybe a video signal. Each sampling circuit 5 _(i) provides, in dependenceon the input data signal, an output signal that is fed to the sourceline S_(i) connected to the transistors T_(ij) of the i^(th) column ofpixels. (FIG. 2 shows a source driver for a full-colour display, so thateach sampling circuit 5 _(i) in fact provides three output signals for acolumn of pixels, one for the red segment of the pixel being addressed,one for the green segment of the pixel, and one for the blue segment ofthe pixel; a source driver for a mono-chromatic display would provideonly a single output signal for a column of pixels.)

FIG. 2 illustrates a single phase source driver, which provides anoutput signal to only one column of pixels at a time. In a first timeperiod, the first output SR0 of the shift register is high and all otheroutputs SR1 . . . SR(m−1) are low, so that only the sampling switches 6in the first sampling circuit 5 ₀ are actuated (i.e., closed) to providean output signal from the sampling circuit 5 ₀. In the next time periodthe second output SR1 of the shift register is high and all otheroutputs SR0 and SR2 . . . SR(m−1) are low, so that only the secondsampling circuit 5 ₁ is actuated to provide an output signal, and so on.This is shown in FIGS. 3( a)-3(h), which illustrate the operation of asingle phase source driver. FIG. 3( a) illustrates the first time periodin which SR0 is high and all other outputs of the shift register 3 arelow, FIG. 3( b) illustrates the second time period in which SR1 is highand all other outputs of the shift register 3 are low, FIG. 3( c)illustrates the penultimate time period in which the penultimate outputSR(m−2) is high and all other outputs of the shift register 3 are low,and FIG. 3( d) illustrates the final time period in which the lastoutput SR(m−1) is high and all other outputs of the shift register 3 arelow. The full line in FIGS. 3( a) to 3(d) represents the i^(th) outputSRi from the shift register, the dotted line labelled V_(SHIFTin)represents suitable input voltages to the i^(th) sampling circuit of thesampler 5 for driving the gate of an n-type TFT, and the broken linelabelled V_(SHIFTip) represents suitable input voltages to the i^(th)sampling circuit of the sampler 5 for driving the gate of a p-type TFT.The bounds of the signals SRi are the voltages V_(SS) and V_(DD) shownin FIG. 2. The bounds of the V_(SHIFT) signals are the voltages V_(SSH)and V_(DDH) shown in FIG. 2. FIGS. 3( e) to 3(h) each represent thesource lines of a column of pixels, and show the data transitions on thesource lines as a row of image data is sampled. The transitions in FIG.3( e) are triggered by the first output SR0 of the shift register shownin FIG. 3( a), the transitions in FIG. 3( f) are triggered by the outputSR1 of the shift register shown in FIG. 3( b), the transitions in FIG.3( g) are triggered by the output SR(m−2) of the shift register shown inFIG. 3( a), and the transitions in FIG. 3( h) are triggered by theoutput SR(m−1) of the shift register shown in FIG. 3( d).

In addition to single phase source drivers, multi-phase source driversare also known. In a multi-phase source driver the image data aresampled N columns at a time, where N (an integer) is the phase of thesystem.

The sampling switches 6 in the sampling circuits 5 _(i) are typicallyTFT analogue switches. In principle, the gates of the sampling switches6 could be driven directly by the output signals SRi from the shiftregister 3. However, it is often desirable to drive the gates of thesampling switches at a voltage that is higher than the upper voltagelevel output by the shift register (in the case of an n-type TFT as asampling switch), or at a voltage that is lower than the lower voltagelevel output by the shift register (in the case of a p-type TFT as asampling switch). An increase in the gate-source voltage applied acrossan n-type TFT sampling switch 6, or a decrease in the gate-sourcevoltage applied across a p-type TFT sampling switch 6, allows the areaof the TFT to be reduced accordingly, so reducing the physical size ofthe source driver. Moreover, smaller sampling switches reduce thecapacitive loading of the video lines 9, thereby reducing the dynamicpower consumed by the source driver.

It is therefore known to provide the level shifter 4 between the shiftregister 3 and the sampler 5, to increase the “swing” of the output ofthe shift register (i.e., to increase the difference between the upperand lower limits of the shift register output). FIG. 2 shows a typicalprior art source driver, in which the level shifter operates fromadditional voltage power supply rails that provide voltages V_(DDH),V_(SSH), where V_(DDH)>V_(DD) and V_(SSH)<V_(SS) (it is assumed thatV_(DD)>V_(SS)), and increase the swing of the shift register signals tothese levels. That is, the level shifter 4 can output a voltage as greatas V_(DDH) or as low as V_(SSH), whereas the shift register can output avoltage only as great as V_(DD) or only as low as V_(SS). However, theneed to provide the additional voltages sources V_(DDH), V_(SSH)complicates the source driver. Moreover, the saving in power consumptionarising from a reduction in the size of the TFT switches 6 may be offsetby the increased power consumption of the level shifters and anyassociated buffer circuits.

Typical level shifter circuits are shown in FIG. 4. When the inputvoltage to the upper half of the circuit is “low” the transistor 37 isoff, but the transistor 39 is on since the output of the inverter 38 is“high” so that the output 40 of the upper half of the circuit isconnected to the V_(SS) supply line. When the input voltage to the upperhalf of the circuit goes “high” the transistor 37 switches on andconnects node 41 to the V_(SS) supply line and so applies a voltageV_(SS) to the gate of the p-transistor 43. This turns the transistor 43on, thereby connecting the output 40 of the upper half of the circuit tothe V_(DDH) supply line. At the same time the p-transistor 42 isswitched off so as to isolate the node 41 from the V_(DDH) supply line.Thus, the upper part of the circuit of FIG. 4 can provide an outputvoltage greater than V_(DD); the lower part of the circuit can similarlyprovide an output voltage lower than V_(SS). These circuits may becascaded to generate the waveforms shown in FIGS. 3( a) to 3(h), or maybe used separately to generate the waveforms shown in FIGS. 5( a) to5(h). The waveforms shown in FIGS. 5( a) to 5(h) correspond to thewaveforms shown in FIGS. 3( a) to 3(h) respectively. The bounds of theV_(SHIFTn) signals in FIGS. 5( a) to 5(d) are the voltages V_(DDH) andV_(SS) shown in FIG. 2, and the bounds of the V_(SHIFTp) signals inFIGS. 5( a) to 5(d) are the voltages V_(DD) and V_(SSH) shown in FIG. 2.

There are a number of prior art documents which describe a source driverof the general type shown in FIG. 2 having a level shifter interposedbetween the shift register and the sampler. In general, these prior artsource drivers suffer from the requirement to provide additional highvoltage power supply rails and control lines for the level shifters. Thehigh voltage rails in particular can significantly increase the powerconsumption of the level shifters and any buffering using these rails.

U.S. Pat. No. 6,765,552 describes a display device with a stage of levelshifters 4 (denoted as “LS”) between a shift register 3 and a samplingcircuit 5, as shown in FIG. 6. However, the level shifters require aseparate power supply voltage.

US patent application No. 2005/0012887 describes a display device withlevel shifters 4 operating from a separate power supply, as shown inFIG. 6. The device uses TFTs of a single type (either n-type or p-type).

US patent application No. 2004/0109526 describes a single-type shiftregister with built-in level shifters (denoted as “LS”) operating from aseparate power supply. The level shifters also require additionalclocking signals.

U.S. Pat. No. 6,483,889 describes a shift register with level shiftersoperated from a separate power supply. This document provides the basisfor the display device of US patent application No. 2005/0012887.

U.S. Pat. No. 5,105,187 describes a shift register with internal voltageboosting. The voltage boosting eliminates the need to provide additionalvoltage supply rails but requires additional boost control lines.

U.S. Pat. No. 5,061,920 describes a source driving scheme which useslevel shifters to shift the logical level of the data to a switchinglevel, implying the use of conventional level shifters.

US 2005/0030276 describes a shift register including control circuitscorresponding to respective blocks. A level shifter of the next stage iscontrolled by one of the outputs of the shift register and one of theoutputs of a series of flip-flop circuits. The level shifter operatesonly for the minimum period required to output the shifted output fromthe current block, thereby reducing the power consumption.

DISCLOSURE OF INVENTION

The present invention provides a drive circuit comprising: a logic blockconnected between a source of a first voltage and a source of a secondvoltage, the first voltage being greater than the second voltage; and atleast one sampling circuit, the or each sampling circuit for sampling ananalogue input and outputting a voltage to a respective output; whereinthe logic block outputs, in use, a respective output signal for eachsampling circuit; wherein the drive circuit further comprises at leastone voltage boost circuit, the or each voltage boost circuit beingassociated with a respective one of the sampling circuits and, uponreceiving the respective signal output from the logic block, generatinga boosted voltage signal and providing the boosted voltage signal to therespective sampling circuit; and wherein each voltage boost circuit isconnected between the source of the first voltage and the source of thesecond voltage.

The voltage boost circuits “boost” the input signals to the samplingcircuits beyond the range defined between the first voltage supply andthe second voltage supply, and can provide a voltage greater than thefirst supply voltage or can provide a voltage lower than the secondsupply voltage, but without requiring additional supply rails andcontrol lines—in a drive circuit of the invention, the voltage boostcircuits are operated by the same supply voltages used to operate thelogic block. The present invention thus allows small sampling switchesto be used in the sampling circuits, since the input signals to thesampling circuits are boosted, but at the same time avoids the need toprovide any additional high voltage power supply rails and control linesfor the voltage boost circuits. As a result, the reduction in powerconsumption obtained by the use of small sampling switches is not offsetby the presence of additional high voltage power supply rails, and adrive circuit of the invention has a low power consumption. A drivecircuit of the invention is thus particularly suitable for use in amobile device, where a low power consumption is highly desirable.

Each voltage boost circuit may comprise a boost capacitor having a firstterminal connectable to the input to a respective sampling circuit; acharging circuit for charging, in a charging period, the boost capacitorto substantially one of the first and second voltages; and a boostcircuit for, in a boosting period, connecting a second terminal of theboost capacitor to a boost bias voltage.

By charging the boost capacitor to the first voltage and then applying aboost bias voltage to the second terminal of the boost capacitor, it ispossible to raise the potential of the first terminal of the boostcapacitor well above the first voltage. Conversely, by charging theboost capacitor to the second voltage and then applying a boost biasvoltage to the second terminal of the boost capacitor, it is possible tolower the potential of the first terminal of the boost capacitor wellbelow the second voltage.

The boost bias voltage may be one of the first and second voltages.

The charging circuit may comprise a first switch connected between thesource of the first voltage and the first terminal of the boostcapacitor.

The boost circuit may comprise a second switch connected between thesource of the first voltage and the second terminal of the boostcapacitor.

The boost circuit may comprise a second switch having a first terminalconnected to the source of the first or second voltage, the secondswitch being controlled by the potential at the first terminal of theboost capacitor; and the first switch may be controlled by the potentialat the second terminal of the second switch.

The boost bias voltage may be a respective output signal from the logicblock.

Each voltage boost circuit may comprise a pass switch for disconnectingthe first terminal of the boost capacitor from an output of the voltageboost circuit during the charging period.

Each voltage boost circuit may further comprise a discharging switch forconnecting the output of the voltage boost circuit to the other of thefirst and second voltages, the discharging switch being controlled to beopen when the pass switch is closed.

The first switch may be a transistor. It may be a diode-connectedtransistor.

The first switch may be controlled by a respective output signal fromthe logic block. For example, the first switch may be capacitivelycoupled to a respective output signal from the logic block.

The logic block may be a shift register.

It should be noted that the term “shift register” can have two differentmeanings. A true “shift register” is a cascade of flip-flop circuitswhich can shift arbitrary data along its length. However, “walking one”types of logic block, which can only shift a single logic “one” alongtheir length, are also commonly referred to as a “shift register”. Theterm “shift register” as used herein is intended to cover both a “trueshift register” (i.e., a logic block which can shift arbitrary dataalong its length), and a “walking one” logic block which can shift onlya single logic “one” along its length.

Each voltage boost circuit may comprise a second pass switch forconnecting the first terminal of the boost capacitor to the output ofthe voltage boost circuit during at least part of the charging period.This allows the output of the voltage boost circuit to be “pre-charged”.Pre-charging of the output of the voltage boost circuit may also beprovided by suitably controlling the first pass switch and the firstdischarging switch, and this enables pre-charging to be provided withoutthe second pass switch.

The output of a voltage boost circuit is connectable to the output of apreceding voltage boost circuit. This allows charge to be shared betweenone voltage boost circuit and the next.

The drive circuit may further comprise a switch for connecting the firstterminal of the boost capacitor to a storage capacitor during the boostphase. The storage capacitor can be used to maintain the potential of avoltage supply rail at the boosted voltage.

The voltage boost circuits may share a common boost capacitor. Use of acommon boost capacitor reduces the number of capacitors required.

Each voltage boost circuit may generate a voltage signal having avoltage greater than the first voltage. Such a voltage is suitable fordriving an n-type sampling switch. Alternatively, each voltage boostcircuit may generate a voltage signal having a voltage lower than thesecond voltage. Such a voltage is suitable for driving a p-type samplingswitch. Alternatively, each voltage boost circuit may generate, at afirst output, a first voltage signal having a voltage greater than thefirst voltage and may generate, at a second output, a second voltagesignal having a voltage lower than the second voltage. Such a voltageboost circuit can drive an n-type sampling switch and a p-type samplingswitch.

A second invention provides a display device comprising a drive circuitof the first aspect.

The drive circuit may comprise a switch for connecting the firstterminal of the boost capacitor to a storage capacitor during the boostphase.

The voltage boost circuits may share a common boost capacitor.

The voltage boost circuit may comprise a second switch having a firstterminal connected to the source of the first or second voltage, thesecond switch being controlled by the potential at the first terminal ofthe boost capacitor; and the first switch may be controlled by thepotential at the second terminal of the second switch.

Each voltage boost circuit may generate a boosted voltage signal havinga voltage greater than the first voltage.

Each voltage boost circuit may generate a boosted voltage signal havinga voltage lower than the second voltage.

Each voltage boost circuit may generate, at a first output, a firstboosted voltage signal having a voltage greater than the first voltageand generates, at a second output, a second boosted voltage signalhaving a voltage lower than the second voltage.

The display device may comprise a plurality of source lines, and eachsource line may be connected to a respective output of the drivecircuit. In this embodiment, the drive circuit of the invention acts asor is part of a source driver for the display device (the source drivermay comprise other circuits in addition to a drive circuit of theinvention).

The display device may comprise a liquid crystal display device, and itmay comprise an active matrix liquid crystal display device.

BRIEF DESCRIPTION OF DRAWINGS

Preferred embodiments of the present invention will now be describedwith reference to the accompanying drawings, in which:

FIG. 1 shows a typical active matrix liquid crystal display;

FIG. 2 is a block diagram of a typical source driver;

FIGS. 3( a) to 3(h) are timing diagrams for signals in the source driverof FIG. 2;

FIG. 4 shows a typical level shifter circuit;

FIGS. 5( a) to 5(h) are timing diagrams for signals in the level shiftercircuit of FIG. 4;

FIG. 6 shows a prior art source driver;

FIG. 7 shows a prior art source driver;

FIG. 8 is a block schematic diagram of a drive circuit of the presentinvention;

FIG. 9( a) shows a voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 9( b) shows timing signals for the circuit of FIG. 9( a);

FIG. 10 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 11 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 12 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 13 is a schematic partial view of a source driver having samplingswitches consisting of n- and p-type TFTs for one pixel column;

FIG. 14 is a schematic partial view of a source driver having samplingswitches consisting only of n-type TFTs for one pixel column;

FIG. 15 is a schematic partial view of a source driver having samplingswitches consisting only of p-type TFTs for one pixel column;

FIGS. 16( a) to 16(d) are timing diagrams for signals in a single-phasedrive circuit of the present invention with pre-charging;

FIG. 17 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 18 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 19 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 20 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 21 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention;

FIG. 22 shows another embodiment of the present invention;

FIG. 23 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention; and

FIG. 24 shows another voltage boost circuit suitable for use in a drivecircuit of the present invention.

BEST MODE FOR CARRYING OUT INVENTION

The present invention will be described primarily with reference to itsapplication as a source driver circuit. However, a drive circuit of theinvention is not limited to use as a source driver circuit but has otherpossible applications.

FIG. 8 is a block schematic diagram of a drive circuit 10 of the presentinvention In this embodiment the drive circuit is a source drivercircuit for use in a display device such as an AMLCD, and each output Oof the drive circuit is connected to a respective source line. Thesource driver 10 contains a logic block 3, a voltage booster 11comprising a plurality of voltage boost circuits 11 _(i) (where i=0, 1,2 . . . (m−1)), and a sampler 5 comprising a plurality of samplingcircuits 5 _(i) (where i=0, 1, 2 . . . (m−1)). The logic block 3 isconnected to first and second voltage supply lines 7, 8 which providefirst and second supply voltages V_(DD), V_(SS) respectively. It will beassumed that V_(DD)>V_(SS). The sampler 5 has input data lines 9 forreceiving an analogue input (for example, an input data signal thatdefines an image to be displayed on a display device; the input datalines 9 may be video lines and the input data signal may be a videosignal). Each sampling circuit 5 _(i) samples the analogue input andprovides, in dependence on the analogue input, an output signal that isfed to a respective output O. In the example of FIG. 8 each respectiveoutput is, as noted above, connected to a source line connected to theswitching elements (e.g. transistors) of the i^(th) column of pixels ofthe display device. (FIG. 8 shows a source driver for a full-colourdisplay, so that each sampling circuit 5 _(i) provides three outputsignals for a column of pixels, one for the red segment of the pixeladdressed, one for the green segment of the pixel, and one for the bluesegment of the pixel; the invention may also provide a source driver fora mono-chromatic display, in which case each of the sampling circuits 5_(i) would provide only a single output signal to each column ofpixels.)

Each of the voltage boost circuits 11 _(i) receive as its input theassociated output SRi from the logic block 3. When the output SRi is“high” it will be equal to the first supply voltage V_(DD), and when theoutput SRi is “low” it will be equal to the second supply voltageV_(SS). The voltage boost circuits “boost” the input signal, and providean output signal that is greater than the first supply voltage V_(DD)(if SRi is “high”) or that is less than the second supply voltage V_(SS)(if SRi is “low”). As explained above, this allows the sampling switches6 of the sampling circuits to be made smaller, thereby reducing thephysical size of the sampling circuits; making the sampling switchessmaller also reduce the capacitive loading of the video lines, therebyreducing the dynamic power consumed by the source driver.

The voltage boost circuits 11 _(i) are connected between the supply line7 that supplies the first supply voltage V_(DD) and the supply line 8that supplies the second supply voltage V_(SS)—that is, the voltageboost circuits 11 _(i) use the same supply voltages as the logic block3. Conventional level shifters have high voltage invertors at theiroutputs to buffer the sampling pulses, but the voltage boost circuits 11do not require these high voltage inverters. The elimination of the highvoltage invertors reduces the power consumption. In addition, chargeleakage in the voltage boost circuits 11 is low and this alsocontributes to a reduction in power consumption. The power consumptionof voltage boost circuits is typically approximately 50% of the powerconsumption of conventional level shifters. Furthermore, the boostedvoltages are usually high enough to allow the size of the TFTs in thesampling circuits to be reduced further, giving a reduction ofapproximately 20% in the dynamic power consumption associated with thevideo lines. Thus, the source driver 10 of the invention has a lowerpower consumption than the prior art source driver of FIG. 2.

Furthermore, since the voltage boost circuits 11 _(i) use the samesupply voltages as the logic block 3 the design of the source driver issimplified. There is no need to provide additional high voltage supplylines or control lines.

In the circuit of FIG. 8 the logic block 3 is a shift register. Theinvention is not, however, limited to use with a shift register but maybe applied to other logic blocks.

FIG. 9( a) is a circuit diagram of one voltage boost circuit 11 _(i)suitable for use in the drive circuit of FIG. 8 for driving n-type TFTs.(A circuit that is complementary to the circuit of FIG. 9( a) may beused for driving p-type TFTs.) The voltage boost circuit 11 _(i)includes a boost capacitor 12, a first terminal of which is connectedvia a charging switch 13 to the supply line 7 that supplies the firstsupply voltage V_(DD). The second terminal of the boost capacitor 12 isconnected to ground via a second switch 14 or to the supply line 7 thatsupplies the first supply voltage V_(DD) via a third switch 15. Thefirst terminal of the boost capacitor 12 is connected via a fourthswitch 16 to the output 17 of the boost circuit. The output 17 of theboost circuit is connected to ground via a fifth switch 18.

FIG. 9( a) also shows a sampling switch 6 of the associated samplingcircuit 5 _(i) with its gate G connected to the output 17 of the voltageboost circuit 11 _(i). The sampling switch is shown as a transistor,with its drain connected to a video line for sampling an input voltageV_(i) on the video line and with its source S connected to a source lineS_(i) to apply an output voltage V_(S) to the source line S_(i).

In operation, in a charging mode, as indicated by arrow 21, the first,second and fifth switches 13, 14, 18 are closed, while the third andfourth switches 15,16 are open. The first and second switches define acharging circuit, and cause current to flow from the supply line 7 forthe first supply voltage (V_(DD)) through the first switch 13, the boostcapacitor 12 and the second switch to ground thereby charging thecapacitor 12 to the first supply voltage V_(DD). In the charging modethe fifth switch 18 is also closed, thereby discharging the output 17and the gate G of the sampling switch to ground.

In the boost mode, the first, second and fifth switches 13, 14, 18 areopen, while the third and fourth switches 15,16 are closed. The secondterminal of the boost capacitor is now connected to the first supplyvoltage V_(DD) and that acts as a boost bias voltage. The secondterminal of the boost capacitor is thus raised in potential, therebyraising the first terminal of the boost capacitor to a potential abovefirst supply voltage V_(DD). That voltage is applied to the output 17 ofthe voltage boost circuit as indicated by arrow 22. In the specificexample of FIG. 9( a), the boost bias voltage is the first supplyvoltage V_(DD) supply line 7 and so the first terminal of the boostcapacitor is raised to a potential that will be approximately 2V_(DD)(but that will be below 2V_(DD) as a consequence of charge sharingbetween the boost capacitor and the capacitance of the gate of thesampling switch, and also as a consequence of charge leakage duringswitching).

The first to fifth switches may be MOS switches. They are actuated bytiming signals T1, T2 having the form shown in FIG. 9( b) and providedby a mode selector circuit 20, with the first, second and fifth switches13,14,18 being closed when the first timing signal T1 is “high” and thethird and fourth switches 15,15 being closed when the second timingsignal T2 is “high”. (FIG. 9( b) shows the duration of the boost periods24 as being relatively short compared to the duration of the chargingperiods, but the relative durations of these periods may be varied fromthose shown in FIG. 9( b).) A circuit of the type shown in FIG. 9( a) isdescribed in U.S. Pat. No. 6,724,239.

FIG. 10 is a circuit diagram of another voltage boost circuit 11 _(i)suitable for use in the drive circuit of FIG. 8. A sampling switch 6 ofa sampling circuit 5 _(i) may be connected to the output 17 of thevoltage boost circuit.

The voltage boost circuit 11 _(i) again comprises a boost capacitor 12.While the output SR_(i) from the shift register 3 is “low”, the firstterminal 23 of the boost capacitor 12 is charged to a voltage of(V_(DD)−V_(tc)), where V_(tc) is the threshold voltage of a chargingtransistor 24 connected between the V_(DD) supply rail 7 and the firstterminal 23 of the boost capacitor 12. The charging transistor 24 is adiode connected transistor, in that its drain is connected to its gate,so that the charging transistor conducts only when the V_(DD) supplyrail 7 is higher than its drain potential by at least the thresholdvoltage V_(tc).

The voltage boost circuit 11 _(i) of FIG. 10 further includes a passswitch 27 for connecting the first terminal 23 of the boost capacitor 12to the output terminal 17, and a discharging switch 28 for connectingthe output terminal 17 to earth. The discharging switch 28 is controlledto be open when the pass switch 27 is closed. In the circuit of FIG. 10this is achieved by embodying one switch as a PMOS transistor andembodying the other switch as an NMOS transistor, and applying the samecontrol signal to the gates of both transistors so that one transistoris on when the other is off. In FIG. 10 the pass switch 27 is embodiedas a PMOS transistor and the discharging switch 28 is embodied as anNMOS transistor

When the output SR_(i) from the shift register 3 goes “high”, the PMOSpass transistor 27 is turned on by a first inverter 25 whose output isconnected to the gate of the PMOS pass transistor 27, thereby connectingthe first terminal 23 of the boost capacitor 12 to the output 17 of thevoltage boost circuit. The first inverter 25 also controls the gate ofthe NMOS discharging transistor 28 which is connected between the output17 and ground potential so that when SRi is “high” the first inverterturns off the NMOS discharging transistor 28 to isolate the output 17from ground potential.

The output from the first inverter 25 is connected via a second inverter26 to the second terminal of the boost capacitor 12. The output of thesecond inverter 26 acts as a boost bias voltage so that, when the outputSR_(i) from the shift register 3 goes “high”, the output of the secondinverter 26 drives up the potential of the second terminal of the boostcapacitor 12 and thereby drives the potential of the first terminal 23of the boost capacitor 12 above its precharge value. The potential ofthe first terminal 23 of the boost capacitor 12, and thereby thepotential at the output 17, can be driven to well above V_(DD). (Whenthe potential of the first terminal 23 of the boost capacitor 12 isboosted above V_(DD), the charging transistor 24 switches off.)

When the output SR_(i) from the shift register 3 subsequently goes“low”, the output from the first inverter 25 turns on the NMOSdischarging transistor 28, thereby connecting the output 17 to groundpotential. At the same time, the PMOS pass transistor 27 is turned off,thereby isolating the output 17 of the voltage boost circuit from thefirst terminal 23 of the boost capacitor 12.

The charging transistor 24 may be an NMOS transistor.

In a modification of the embodiment, the charging transistor 24 may bereplaced by a diode.

A circuit of the type shown in FIG. 10 is described in U.S. Pat. No.6,330,196.

FIG. 11 is a circuit diagram of another voltage boost circuit 11 _(i)suitable for use in the drive circuit of FIG. 8. A sampling switch 6 ofa sampling circuit 5 _(i) may be connected to an output 17, 17′ of thevoltage boost circuit.

The operation of the top half of the voltage boost circuit of FIG. 11 issimilar to the operation of the voltage boost circuit of FIG. 10.Compared with the circuit of FIG. 10, the NMOS device 24 charging theboost capacitor 12 is no longer configured as a diode—instead, anadditional capacitor 29 and switch 30 control the gate voltage of theNMOS device 24 charging the boost capacitor 12. One terminal of theadditional capacitor 29 is connected to the switch 30, and the otherterminal of the additional capacitor 29 receives the signal SRi, whichis the inverse of the i^(th) shift register output signal SRi, as input.The additional switch 30 is controlled by the potential at the firstterminal 23 of the boost capacitor. In the embodiment of FIG. 11 theadditional switch 30 is embodied as an NMOS device, and the gate of theadditional NMOS device 30 is connected to the first terminal 23 of theboost capacitor. The gates of the PMOS pass transistor 27 and the NMOSdischarging transistor 28 are each controlled by the signal SRi (wherethe signal SRi is “high” when the signal SRi is “low”, and vice-versa).

When the output SRi from the shift register 3 is “low”, the NMOS device24 is switched on because a positive voltage is applied to its gate viathe additional input 36, to which the signal SRi is applied, and theadditional capacitor 29. The first terminal 23 of the boost capacitor 12is charged up to the higher supply voltage V_(DD) while the secondterminal of the boost capacitor is at a low potential. The output 17 isconnected to the supply rail 8 for the lower supply voltage V_(SS) viathe NMOS discharging transistor 28, which is turned on since its gate isdriven by SRi. The first terminal 23 of the boost capacitor 12 isisolated from the output 17 since the PMOS pass transistor 27 is off.

When the output SR_(i) from the shift register goes “high”, the outputSR_(i) from the shift register 3 drives up the potential of the secondterminal of the boost capacitor 12 and thereby drives the potential ofthe first terminal 23 of the boost capacitor 12 above its prechargevalue. The potential of the first terminal 23 of the boost capacitor 12,and thereby the potential at the output 17, can be driven to well abovethe higher supply voltage V_(DD). When SRi goes “high”, the NMOSdischarging transistor 28 is turned off to isolate the output 17 fromthe supply rail 8 for the lower supply voltage V_(SS), and the PMOS passtransistor 27 is turned on to connect the first terminal 23 of the boostcapacitor to the output 17. Thus, an output voltage V_(BOOSTni) that iswell above the upper supply voltage V_(DD) can be delivered to theoutput terminal 17 for operating an n-type sampling switch.

The bottom half of the voltage boost circuit 11 _(i) of FIG. 11 isconstructed and operates in a complementary manner to the upper half ofthe circuit. A component in the bottom half of the voltage boost circuit11 _(i), is identified by the same reference number as its complementarycomponent in the upper half of the circuit, with the addition of an--′--. Thus, component 24′ in the lower half of the voltage boostcircuit is a PMOS device for connecting the first plate 23′ of the boostcapacitor 12′ to the supply rail for the lower supply voltage V_(SS).

When the output SRi from the shift register 3 is “low”, the PMOS device24′ in the lower half of the circuit is switched on because a lowvoltage is applied to its gate via the additional input 36′, to whichthe signal SRi is applied, and the additional capacitor 29′, and thefirst terminal 23′ of the boost capacitor 12′ is charged to the lowersupply voltage V_(SS) while the second terminal of the boost capacitoris at a high potential. The output 17′ of the lower half of the circuitis connected to the supply rail 7 for the higher supply voltage V_(DD)via the PMOS discharging transistor 28′, which is turned on since itsgate is driven by SRi. The first terminal 23′ of the boost capacitor 12′is isolated from the output 17′ since the NMOS pass transistor 27′ isoff.

When the output SRi from the shift register goes “high”, the outputSR_(i) from the shift register 3 drags down the potential of the secondterminal of the boost capacitor 12′ and thereby drags the potential ofthe first terminal 23′ of the boost capacitor 12′ below its prechargevalue. The potential of the first terminal 23′ of the boost capacitor12′, and thereby the potential at the output 17′, can be dragged down towell below the lower supply voltage V_(SS). When SRi goes “high”, thedischarging transistor 28′ is turned off to isolate the output 17′ fromthe supply rail 7 for the higher supply voltage V_(DD), and the passtransistor 27′ is turned on to connect the first terminal 23′ of theboost capacitor to the output 17′. Thus, the bottom half of the voltageboost circuit 11 _(i) of FIG. 11 generates a “boosted” voltageV_(BOOSTpi) that is below the lower supply voltage V_(SS) and that issuitable for operating a p-type switch.

FIG. 12 is a circuit diagram of another voltage boost circuit 11 _(i)suitable for use in the drive circuit of FIG. 8. A sampling switch 6 ofa sampling circuit 5 _(i) may be connected to an output 17, 17′ of thevoltage boost circuit.

The top and bottom halves of the voltage boost circuit of FIG. 12 aresimilar to the top and bottom halves, respectively, of the voltage boostcircuit of FIG. 11. Compared with the circuit of FIG. 11, the node 31 atthe opposite side of the NMOS discharging transistor 28 is not connecteddirectly to the supply rail 8 for the lower supply voltage V_(SS) but isinstead connected to the supply rail 8 for the lower supply voltageV_(SS) by a further PMOS transistor 33; the node 31 is also connectedvia a further capacitor 32 to the second terminal of the boost capacitor12.

When the output SRi of the shift register 3 is “low”, the boostcapacitor charges up as described with reference to FIG. 11 above.

When the output SRi from the shift register goes “high”, the outputSR_(i) from the shift register 3 drives up the potential of the secondterminal of the boost capacitor 12 and thereby drives the potential ofthe first terminal 23 of the boost capacitor 12 above its prechargevalue. The potential of the first terminal 23 of the boost capacitor 12,and thereby the potential at the output 17 of the upper half of thecircuit, can be driven to well above the higher supply voltage V_(DD) asdescribed with reference to FIG. 11 above.

When the output SRi from the shift register is “high”, the gate of thefurther PMOS transistor 33 is “low” (since the gate is controlled bySRi), and the further PMOS transistor 33 is in a diode configuration(both gate and drain are connected to the lower supply voltage V_(SS)).Therefore, the further capacitor 32 is charged to V_(DD)−V_(thp), whereV_(thp) is the threshold voltage of transistor 33. When the output SRifrom the shift register goes “low” the further PMOS transistor 33 isturned off, and node 31 is boosted to a potential less than the lowersupply voltage V_(SS). This voltage is passed to the output 17 since theNMOS discharging transistor 28 is on (as its gate is controlled by SRi).Thus, when the output SRi of the shift register is “low”, the voltage atthe output 17 of the upper half of the circuit will not be the lowersupply voltage V_(SS) but will be a voltage lower than the lower supplyvoltage V_(SS).

The bottom half of the voltage boost circuit 11 _(i) of FIG. 12 isconstructed and operates in a complementary manner to the upper half ofthe circuit. A component in the bottom half of the voltage boost circuit11 _(i), is identified by the same reference number as its complementarycomponent in the upper half of the circuit, with the addition of an--′--. When the output SRi from the shift register is “high”, the bottomhalf of the voltage boost circuit 11 _(i) of FIG. 12 generates a“boosted” voltage V_(BOOSTpi) that is below the lower supply voltageV_(SS) and that is suitable for operating a p-type switch. When theoutput SRi from the shift register is “low”, the voltage at the outputterminal 17′ of the bottom half of the voltage boost circuit 11 _(i) ofFIG. 12 greater than the higher supply voltage V_(DD). (When the outputSRi from the shift register is “high”, the gate of the further NMOStransistor 33′ is “high” (since the gate is controlled by SRi), and thefurther NMOS transistor 33′ is in a diode configuration (both gate anddrain are connected to the upper supply voltage V_(DD)). Therefore, thefurther capacitor 32′ is charged to V_(DD)−V_(thn), where V_(thn) is thethreshold voltage of transistor 33′.)

A drive circuit 10 of the present invention may be incorporated on thesubstrate of the display device such as, for example, an active matrixdisplay device. A drive circuit 10 of the present invention may replacethe source driver 2 of the AMLCD of FIG. 1.

A drive circuit 10 of the present invention may have sampling circuits 5_(i) that contain sampling switches 6 that consist of both n-type TFTsand p-type TFTs. This is illustrated in FIG. 13, which is a partial viewof a source driver according to the invention showing one samplingcircuit 5 _(i). As can be seen in FIG. 13, each sampling switch 6consists of one n-type TFT 34 and p-type TFT 35. The source of then-type TFT 34 is connected to the source of the p-type TFT 35 at node S,and the drain of the n-type TFT 34 is connected to the drain of thep-type TFT 35 at node D. Node D is connected to a video line, and node Sis connected to a source line. FIG. 13 shows a sampling circuit for usewith a full colour display so that each sampling circuit 5 _(i) hasthree switches 6 to provide three output signals for a column of pixels,one for the red segment of the addressed pixel, one for the greensegment of the pixel, and one for the blue segment of the pixel; theinvention may also provide a source driver for a mono-chromatic display,in which case each of the sampling circuits 5 _(i) would provide containonly a single switch 6 to provide a single output signal to each columnof pixels.

The source driver of FIG. 13 require a voltage boost circuit that canprovide both a voltage V_(BOOSTni) that is greater than the highersupply voltage V_(DD) and a voltage V_(BOOSTpi) that is lower than thelower supply voltage V_(SS). The voltage V_(BOOSTni) that is greaterthan the higher supply voltage V_(DD) is supplied to the gate of then-type TFT 34, and the voltage V_(BOOSTpi) that is lower than the lowersupply voltage V_(SS) is supplied to the gate of the p-type TFT 35. Avoltage boost circuit as shown in FIG. 11 or 12 could, for example, beused in the source driver of FIG. 13, with the upper half of the circuitproviding the voltage V_(BOOSTni) to the gate of the n-type TFT 34 andthe lower half of the circuit providing the voltage V_(BOOSTpi) to thegate of the p-type TFT 35.

It is possible to construct voltage boost circuits that arecomplementary to the voltage boost circuits of FIGS. 9( a) and 10, andwhich provide a voltage V_(BOOSTpi) suitable for switching a p-type TFTin a sampling circuit, where V_(BOOSTpi) is lower than the lower supplyvoltage V_(SS)

A drive circuit 10 of the present invention may alternatively havesampling circuits 5 _(i) that contain sampling switches 6 that consistonly of n-type TFTs. This is illustrated in FIG. 14, which is a partialview of a source driver according to the invention showing one samplingcircuit 5 _(i). As can be seen in FIG. 14, each sampling switch 6consists of one n-type TFT 34. The source of the n-type TFT 34 isconnected to a source line, and the drain of the n-type TFT 34 isconnected to a video line. FIG. 14 shows a sampling circuit for use witha full colour display so that each sampling circuit 5 _(i) has threeswitches 6 to provide three output signals for a column of pixels, onefor the red segment of the addressed pixel, one for the green segment ofthe pixel, and one for the blue segment of the pixel; the invention mayalso provide a source driver for a mono-chromatic display, in which caseeach of the sampling circuits 5 _(i) would provide contain only a singleswitch 6 to provide a single output signal to each column of pixels.

The source driver of FIG. 14 require a voltage boost circuit that canprovide a voltage V_(BOOSTni) that is greater than the higher supplyvoltage V_(DD), and this voltage V_(BOOSTni) is supplied to the gate ofthe n-type TFT 34. A voltage boost circuit as shown in FIG. 9( a) or 10,or the upper half of a voltage boost circuit as shown in FIG. 11 or 12could, for example, be used in the source driver of FIG. 14.

A drive circuit 10 of the present invention may alternatively havesampling circuits 5 _(i) that contain sampling switches 6 that consistonly of p-type TFTs. This is illustrated in FIG. 15, which is a partialview of a source driver according to the invention showing one samplingcircuit 5 _(i). As can be seen in FIG. 15, each sampling switch 6consists of one p-type TFT 35. The source of the p-type TFT 35 isconnected to a source line, and the drain of the p-type TFT 35 isconnected to a video line. FIG. 14 shows a sampling circuit for use witha full colour display so that each sampling circuit 5 _(i) has threeswitches 6 to provide three output signals for a column of pixels, onefor the red segment of the addressed pixel, one for the green segment ofthe pixel, and one for the blue segment of the pixel; the invention mayalso provide a source driver for a mono-chromatic display, in which caseeach of the sampling circuits 5 _(i) would provide contain only a singleswitch 6 to provide a single output signal to each column of pixels.

The source driver of FIG. 15 require a voltage boost circuit that canprovide a voltage V_(BOOSTpi) that is lower than the lower supplyvoltage V_(SS), and this voltage V_(BOOSTpi) is supplied to the gate ofthe p-type TFT 35. The lower half of a voltage boost circuit as shown inFIG. 11 or 12 could, for example, be used in the source driver of FIG.15.

The embodiments of the invention described above are single-phase drivercircuits. The invention is not, however, limited to a single-phase drivecircuit but may be applied to an N-phase drive circuit where N>1.

The present invention may also be applied to a drive circuit that usespre-charging to conserve power. Pre-charging increases the boostedvoltages that can be provided, so that the size of the sampling switchescan be reduced further thereby further reducing the power consumption.FIGS. 16( a) to 16(d) illustrate pre-charging for a single-phase (N=1)drive circuit. FIGS. 16( a) to 16(d) show voltage waveforms forapplication to the gates of sampling switches in, respectively, thefirst (i=0), second (i=1), penultimate (i=m 2) and last (i=m−1) samplingcircuits. In each case, the three waveforms shown are the ith output SRifrom the shift register (full line), the voltage applied to the gate ofan n-type transistor included in sampling switches in the i^(th)sampling circuit (dotted line), and the voltage applied to the gate of ap-type transistor included in sampling switches in the i^(th) samplingcircuit (broken line).

In time period T1, the SR(m−1) output from the shift register is “high”and all other outputs from the shift register are “low”. The gates ofthe sampling switches of the (m−1)^(th) sampling circuit are charged totheir full voltages at the start of time period T1, as indicated by thewaveforms of FIG. 16( d) representing the voltages applied to the gatesof n-type and p-type transistors included in sampling switches in the(m−1)^(th) sampling circuit. The voltage applied to the gate of ann-type transistor included in sampling switches in the (m−1)^(th)sampling circuit is charged to it greatest value at the start of thetime period T1, and the voltage applied to the gate of a p-typetransistor included in sampling switches in the (m−1)^(th) samplingcircuit is charged to it lowest value at the start of the time periodT1.

Also in the time period T1, the gates of the sampling switches of thenext sampling circuit—namely the i=0 sampling circuit—are pre-charged toan intermediate voltage (e.g., the higher supply voltage V_(DD) in acircuit intended to drive an n-type transistor or the lower supplyvoltage V_(SS) in a circuit intended to drive a p-type transistor). Thisis shown in the waveforms of FIG. 16( a) representing the voltagesapplied to the gate of n-type and p-type transistors included insampling switches in the i=0 sampling circuit.

Similarly, in the next time period T2 the gates of the sampling switchesof the i=0 sampling circuit are charged to their full voltages at thestart of time period T2, and the gates of the sampling switches of thenext sampling circuit—namely the i=1 sampling circuit—are pre-charged toan intermediate voltage.

Pre-charging may also be applied in an N-phase drive circuit. For anN-phase system, whilst image data is sampled for N pixel columns in onetime period, the gates of TFT sampling switches for the next N pixelcolumns are pre-charged to an intermediate voltage in the same timeperiod. Once sampling for the first N pixel columns has been completed,the gates of TFT sampling switches for the next N pixel columns aredriven to the full boost levels at the start of the next time period,and image data is sampled for these pixel columns. Also in this nexttime period, the gates of the TFT sampling switches for the next N pixelcolumns are pre-charged.

FIG. 17 shows a further voltage boost circuit suitable for use in adrive circuit of the invention. The voltage boost circuit of FIG. 17 canprovide pre-charging. The voltage boost circuit of FIG. 17 is based onthe voltage boost circuit of FIG. 11. The upper part of the voltageboost circuit of FIG. 17 includes a second pass switch 44 connected inparallel with the first pass switch 27 between the first terminal 23 ofthe boost capacitor 12 and the output 17. The second pass switch 44 iscontrolled so as to be closed for at least part of period in which theboost capacitor 12 is being charged up to a potential of the highersupply voltage V_(DD) so that the output 17 is pre-charged. In theembodiment of FIG. 17 the second pass switch is a PMOS transistor. Thegate of the second pass PMOS transistor 44 is controlled by the signalSR(i−1), which is the inverse of the (i−1)^(th) output of the shiftregister.

The output of the upper part of the voltage boost circuit of FIG. 17 isisolated from the lower supply voltage V_(SS) during both the (i−1)^(th)and i^(th) periods (i.e., the periods in which (i−1)^(th) and i^(th)outputs from the shift register are “high”). In the circuit of FIG. 17this is achieved by providing a second discharging switch 45 connectedin series with the first discharging switch 28 between the lower supplyvoltage V_(SS) and the output 17, with the second discharging switch 45arranged to be open when the (i−1)^(th) output SR(i−1) of the shiftregister is “high”. In FIG. 17 the second discharging switch 45 isembodied as an NMOS transistor, and the gate of the second NMOSdischarging transistor 45 is controlled by the signal SR(i−1).

When the i^(th) output SRi of the shift register is “low”, the boostcapacitor 12 is charged up to the higher supply voltage V_(DD) asdescribed with reference to FIG. 11. In the period when the (i−1)^(th)output SR(i−1) of the shift register is “high”, the second passtransistor 44 is closed so that the output 17 of the upper half of thecircuit is connected to the first terminal 23 of the boost capacitor.Since the i^(th) output SRi of the shift register is “low”, the firstterminal 23 of the boost capacitor is connected to the V_(DD) supplyrail 7 via the transistor 24; thus, the output 17 of the upper half ofthe circuit is pre-charged to the higher supply voltage V_(DD).

When the i^(th) output SRi of the shift register goes “high”, thepotential at the first terminal 23 of the boost capacitor is boostedabove the higher supply voltage V_(DD), as described with reference toFIG. 11 above. The second PMOS pass transistor 44 is now open but thefirst PMOS pass transistor is closed, so that the first terminal 23 ofthe boost capacitor is connected to the output 17 of the upper half ofthe circuit and the boosted voltage is applied to the output 17.

The output 17 of the upper half of the circuit is isolated from thelower supply voltage V_(SS) when either the (i−1)^(th) output SR(i−1) ofthe shift register or the i^(th) output SRi of the shift register ishigh, as one or other of the NMOS discharging transistors will be “off”.If SR(i−1) and SRi are both low, both NMOS discharging transistors 28,45will be “on” and the output 17 of the upper half of the circuit isconnected to the lower supply voltage V_(SS) supply.

The upper half of the voltage boost circuit of FIG. 17 thus provides anoutput voltage of the higher supply voltage V_(DD) if the (i−1)^(th)output SR(i−1) of the shift register is “high” to provide pre-charging,provides an output voltage boosted above the higher supply voltageV_(DD) if the i^(th) output SRi of the shift register is “high”, andprovides an output voltage of the lower supply voltage V_(SS) otherwise.

The lower part of the voltage boost circuit of FIG. 17 similarlyincludes a second pass switch 44′ connected in parallel with the firstpass switch 27′ between the first terminal 23′ of the boost capacitor12′ and the output 17′. It also includes a second discharging switch 45′connected in series with the first discharging switch 28′ between theV_(DD) supply voltage and the output 17′. In the embodiment of FIG. 17the second pass switch 44′ is an NMOS transistor, and the seconddischarging switch 45′ is a PMOS transistor. The gates of the secondpass transistor 44′ and the second discharging transistor 45′ arecontrolled by the signal SR(i−1). The lower half of the voltage boostcircuit of FIG. 17 can provide an output voltage of the lower supplyvoltage V_(SS) if the (i−1)^(th) output SR(i−1) of the shift register is“high” to provide pre-charging, an output voltage boosted below thelower supply voltage V_(SS) if the i^(th) output SRi of the shiftregister is “high”, and provides an output voltage of the upper supplyvoltage V_(DD) at other times.

The voltage boost circuit of FIG. 17 may be used in a single phasesystem or a multi-phase system. It may be used with a shift registerthat has overlapping outputs, or with a shift register for which onlyone shift register output is high at any time.

FIG. 18 shows a further voltage boost circuit suitable for use in adrive circuit of the invention. The voltage boost circuit of FIG. 18 canprovide pre-charging. The voltage boost circuit of FIG. 18 is based onthe voltage boost circuit of FIG. 11.

In the upper half of the voltage boost circuit of FIG. 18, the passswitch 27 and the discharging switch 28 are not controlled directly byan output signal from the shift register output, but are controlled bythe output signal X from a logic circuit 54. The logic circuit 54provides an output that turns the pass switch 27 on and the dischargingswitch 28 off if either one of the shift register output signals SR(i−1)and SRi is “high”, and that turns the pass switch 27 off and thedischarging switch 28 on otherwise. This allows the output 17 to bepre-charged when the shift register output signal SR(i−1) is “high”.

In the circuit shown in FIG. 18, the pass switch 27 and the dischargingswitch 28 are embodied as a PMOS transistor and an NMOS transistorrespectively. The logic circuit 54 thus provides an output that is “low”if either one of the shift register output signals SR(i−1) and SRi is“high” and that is “high” otherwise. The logic circuit 54 may beembodied as a NOR gate having as its inputs the shift register outputsignals SR(i−1) and SRi, as shown in FIG. 18.

Similarly, in the lower half of the voltage boost circuit of FIG. 18,the pass switch 27′ and the discharging switch 28′ are not controlleddirectly by an output signal from the shift register output, but arecontrolled by the output signal V from a second logic circuit 54′. Thesecond logic circuit 54′ provides an output signal V that turns the passswitch 27′ on and the discharging switch 28′ off if either one of theshift register output signals SR(i−1) and SRi is “high”, and that turnsthe pass switch 27′ off and the discharging switch 28′ on otherwise.This allows the output 17′ to be pre-charged when the shift registeroutput signals SR(i−1) is “high”.

In the circuit shown in FIG. 18, the pass switch 27′ and the dischargingswitch 28′ are embodied as an NMOS transistor and a PMOS transistorrespectively. The logic second circuit 54′ thus provides an output thatis “high” if either one of the shift register output signals SR(i−1) andSRi is “high” and that is “low” otherwise. The logic circuit 54′ may beembodied as a NAND gate having as its inputs the shift register outputsignals SR(i−1) and SRi, as shown in FIG. 18.

A further embodiment of the invention uses charge sharing to conservecharge and power. For an N-phase system, the charge on the gates of TFTsampling switches for a set of N pixel columns are, once sampling forthese N pixel columns has been completed, passed to the gates of TFTsampling switches for the following N pixel columns. The effect is thatcharge passes from one set of sampling switches to another, therebyproviding a further reduction in power consumption.

FIG. 19 shows a further voltage boost circuit suitable for use in adrive circuit of the invention. The voltage boost circuit of FIG. 19 canprovide charge sharing. The voltage boost circuit of FIG. 19 is based onthe voltage boost circuit of FIG. 11, but the output 17 of the upperhalf of the circuit is connectable to the output 47 of the upper half ofthe voltage boost circuit driving a preceding source line (labelled“V_(BOOSTn(i−1))” in FIG. 19). Similarly, the output 17′ of the lowerhalf of the circuit is connectable to the output 47′ of the lower halfof the voltage boost circuit driving the preceding source line (labelled“V_(BOOSTp(i−1))” in FIG. 19). In FIG. 19 the outputs of the voltageboost circuit are connectable to the respective outputs of theimmediately preceding source line, so that if the voltage boost circuitof FIG. 19 is for the m^(th) source line the outputs 47,47′ are theoutputs of the voltage boost circuit for the (m−1)^(th) source line.

It is necessary for the output 17 of the voltage boost circuit to beisolated from the lower supply voltage V_(SS) in the (i−1)^(th) ori^(th) time periods. In the circuit of FIG. 19 this is achieved byproviding the upper part of the voltage boost circuit with a seconddischarging switch 45 connected in series with the first dischargingswitch 28 between the lower supply voltage V_(SS) supply and the output17. The first and second discharging switches are arranged such that oneof them is open in the (i−1)^(th) time period and such that at least oneof them is open in the i^(th) time period. In the embodiment of FIG. 19the second discharging switch 45 is embodied as a second NMOStransistor, and the gate of the second NMOS discharging transistor 45 iscontrolled by the signal SR i−1. In this embodiment, the output 17 ofthe upper half of the circuit is connected to the V_(SS) supply voltageunless either one of the (i−1)^(th) output SR(i−1) of the shift registeror the i^(th) output SRi of the shift register is “high”.

The output 17 of the upper half of the circuit is connected via a switch46 to the output 47 of the upper part of the voltage boost circuit forthe preceding source line (i.e., the (m−1) source line. The switch 46 iscontrolled by a control signal T₁ such that the switch 46 is closed foreither all or part of the time period when the (i−1)^(th) output SR(i−1)of the shift register is “high”.

When the i^(th) output SRi from the shift register is “low”, the firstterminal 23 of the boost capacitor 12 is connected the V_(DD) supplyline 7 via the transistor 24, as described above with reference to FIG.11.

In the period when the (i−1)^(th) output SR(i−1) of the shift registeris “high”, the output 17 of the upper half of the circuit is isolatedfrom the lower supply voltage V_(SS) since the second NMOS dischargingtransistor 45 is off. The switch 46 is controlled to be closed in thetime period when the (i−1)^(th) output SR(i−1) of the shift register ishigh, so that charge can pass from the output 47 of the upper part ofthe voltage boost circuit for the preceding source line to the output17. (In the time period when the (i−1)^(th) output SR(i−1) of the shiftregister is “high” a boosted voltage will be applied to the output 47 ofthe upper part of the voltage boost circuit for the preceding sourceline, so that the output 47 of the upper part of the voltage boostcircuit for the preceding source line is at a higher potential than theoutput 17; charge will therefore flow to the output 17 from the output47 of the upper part of the voltage boost circuit for the precedingsource line.)

When the i^(th) output SRi of the shift register is “high”, a boostedoutput voltage is applied to the output 17 of the upper half of thecircuit, as described above with reference to FIG. 11. The switch 46 isopen so as to isolate the output 17 from the output 47 of the upper partof the voltage boost circuit for the preceding source line, but anotherswitch (not shown) is closed so as to connect the output 17 to theoutput of the upper part of the voltage boost circuit (not shown) forthe following source line (i.e., the (m+1)^(th) source line). In thisway, charge can pass along a row of pixels, from one set of samplingswitches to the next.

The lower part of the voltage boost circuit of FIG. 19 is complementaryto the upper half. It includes a second discharging switch 45′ connectedin series with the first discharging switch 28′ between the V_(DD)supply voltage and the output 17′ of the lower part of the circuit. InFIG. 19 the second discharging switch is embodied as a PMOS transistor,and the gate of the second PMOS discharging transistor 45 is controlledby the signal SR(i−1). The output 17′ of the lower half of the circuitis connectable via a switch 46′ to the output 47′ of the lower part ofthe voltage boost circuit for the preceding source line (i.e., the (m−1)source line. The switch 46 is controlled by the signal T₁. The output17′ of the lower half of the circuit is also connected via a switch (notshown) to the output of the lower part of the voltage boost circuit (notshown) for the following source line (i.e., the (m+1)^(th) source line).

In FIG. 19 the output of a voltage boost circuit is connected to theoutput of the voltage boost circuit for an immediately preceding sourceline, so that the output of a voltage boost circuit for the m^(th)source line is connectable to the output of the voltage boost circuitfor the (m−1)^(th) source line. In principle, the output of a voltageboost circuit need not be connected to the output of the voltage boostcircuit for the immediately preceding source line; for example, theoutput of the voltage boost circuit for the m^(th) source line could beconnectable to the output of the voltage boost circuit for the(m−2)^(th) source line.

FIG. 20 shows a further voltage boost circuit suitable for use in adrive circuit of the invention. The voltage boost circuit of FIG. 20can, in addition to providing a boosted output voltage, also charge oneor more reservoir capacitors. The reservoir capacitor(s) may be used togenerate a high voltage (for example V_(DDH)) from the boosted outputvoltage V_(boostni) and/or generate a low voltage (for example V_(SSH))from the boosted output voltage V_(boostpi), and supply the or eachvoltage to respective voltage supply rails 52,52′.

The voltage boost circuit of FIG. 20 is based on the voltage boostcircuit of FIG. 11. The first terminal of the boost capacitor 12 in theupper half of the circuit is connected to a first voltage supply rail 52via a switch 48. The switch 48 is arranged to be closed in the boostperiod in which the first terminal of the boost capacitor 12 is boostedabove the supply voltage V_(DD). In the circuit of FIG. 20, this is doneby embodying the switch 48 as a PMOS device whose gate is controlled bythe i^(th) output signal SRi from the shift register. Thus, when thei^(th) output SRi from the shift register goes “high” and the potentialof the first terminal of the boost capacitor 12 is boosted above thehigher supply voltage V_(DD), in the manner described with reference toFIG. 11 above, the switch 48 is closed to connect the first terminal ofthe boost capacitor 12 to the first voltage supply rail 52, therebysupplying a boosted output voltage (for example V_(DDH)) to the firstvoltage supply rail 52. One or more storage capacitors C_(A) areconnected between the first voltage supply rail 52 and a fixed referencevoltage, for example the lower supply voltage V_(SS).

Similarly, the first terminal 23′ of the boost capacitor 12′ in thelower half of the voltage boost circuit of FIG. 20 is connected to asecond voltage supply rail 52′ via a switch 48′. The switch 48′ isarranged to be closed when the first terminal 23′ of the boost capacitor12′ is boosted below the lower supply voltage V_(SS). In the circuit ofFIG. 20, this is done by embodying the switch 48′ as an NMOS devicewhose gate is controlled by the signal SRi. Thus, when the output SRifrom the shift register goes “high” and the potential of the firstterminal 23′ of the boost capacitor 12′ is boosted below V_(SS), theswitch 48′ is closed to connect the first terminal 23′ of the boostcapacitor 12′ to the second voltage supply rail 52′, thereby supplying aboosted output voltage (for example V_(SSH)) to the second voltagesupply rail 52. One or more storage capacitors C_(B) are connectedbetween the second voltage supply rail 52′ and a fixed referencevoltage, for example the lower supply voltage V_(SS).

The storage capacitors C_(A), C_(B) maintain the first and secondvoltage supply rails 52,52′ at the boosted voltages (eg, V_(DDH),V_(SSH)) respectively. The voltage boost circuit of this embodiment canbe said to act as a charge pump. The voltage supply rails 52,52′ thusact as high voltage supply rails, and circuits to be driven may beconnected between the first voltage supply rail 52 and the secondvoltage supply rail 52′ as indicated at circuit 49, and/or between thefirst voltage supply rail 52 and the reference voltage (for example thelower supply voltage V_(SS)) as indicated at circuit 50, and/or betweenthe second voltage supply rail 52′ and the reference voltage (forexample the lower supply voltage V_(SS)) as indicated at circuit 51.

Preferably, the voltage boost circuit for each source line is connectedto the first and second voltage rails 52,52′ in the manner shown in FIG.20.

In principle, the voltage boost circuit of FIG. 20 could be providedwith only the first voltage supply rail 52, the associated switch 48,and the associated storage capacitor C_(A), or with only the secondvoltage supply rail 52′, the associated switch 48′, and the associatedstorage capacitor C_(B).

FIG. 21 shows a further voltage boost circuit suitable for use in adrive circuit of the present invention. The voltage boost circuit ofFIG. 21 has 2 m outputs, of which m outputs provide a boosted voltagegreater than the higher supply voltage V_(DD) and the other m outputsprovide a boosted voltage less than the lower supply voltage V_(SS). Thevoltage boost circuit is thus able to drive sampling switches associatedwith m source lines. However, the voltage boost circuit of FIG. 21 hasonly two boost capacitors 12, 12′ (one in the upper half of the circuitand one in the lower half of the circuit).

The upper half of the voltage boost circuit of FIG. 21 comprises a boostcapacitor 12, the first terminal 23 of which is connectable to thesupply rail 7 for the upper supply voltage V_(DD) by a switch 24. In theembodiment shown, the switch 24 that controls charging of the boostcapacitor 12 is an NMOS device with gate voltage controlled by anadditional capacitor 29 and NMOS device 30 as in FIG. 11.

The upper half of the voltage boost circuit of FIG. 21 further comprisesa plurality of first control circuits C_(i), where i=0, 1, 2, (m−1).Each of the first control circuits is for controlling the voltageapplied to a respective output O_(i) of the voltage boost circuit. Eachfirst control circuit comprises a pass switch P_(i) for connecting thefirst terminal 23 of the boost capacitor to the respective output and adischarging switch N_(i) for connecting the respective output O_(i) to alow voltage source, in this embodiment to the supply rail for the lowersupply voltage V_(SS). In the embodiment of FIG. 21, the pass switchP_(i) is embodied as a PMOS transistor and the discharging switch N_(i)is embodied as an NMOS transistor whose gate is controlled by theinverse SRi of i^(th) output signal of the shift register.

The voltage applied to the gate of the PMOS pass transistor P_(i) issupplied by a respective second control circuit K_(i). Each secondcontrol circuit comprises a second pass switch T_(i) for connecting thegate terminal of the respective PMOS pass transistor P_(i) to the upperterminal 53 of the additional capacitor 29 and a second dischargingswitch D_(i) for connecting the gate terminal of the respective PMOSpass transistor P_(i) to a low voltage source, in this embodiment to thesupply rail for the lower supply voltage V_(SS). In the embodiment ofFIG. 21, the second pass switch T_(i) is embodied as a PMOS transistorwhose gate is connected to the first terminal 23 of the boost capacitorand the second discharging switch D_(i) is embodied as an NMOStransistor whose gate is controlled by the i^(th) output SRi of theshift register.

A signal SRmux is applied to the second terminal of the boost capacitor12. The signal SRmux is a multiplex of the individual output signals SR0. . . SR(m−1) from the shift register, so that SRmux is “high” if anyone of the individual output signals SR0 . . . SR(m−1) from the shiftregister is “high” and is “low” only if every one of the individualoutput signals SR0 . . . SR(m−1) from the shift register is “low”. Moreformally, the signal SRmux is given by SRmux=SR0 OR SR1 OR . . .SR(m−1).

When all the outputs signals SRi from the shift register are “low”, thetransistor 24 is on since SRmux is high, and the first terminal of theboost capacitor 23 is charged to the higher supply voltage V_(DD). Whenthe i^(th) output SRi from the shift register goes “high”, the signalSRmux also goes “high”, and the first terminal of the boost capacitor 12is boosted above the higher supply voltage V_(DD), in the mannerdescribed for previous embodiments. At this time, since the i^(th)output SRi from the shift register is “high”, the second dischargingswitch D_(i) in the i^(th) second control circuit K_(i) is switched ONthereby causing the second control circuit K_(i) to apply the lowersupply voltage V_(SS) to the gate of the PMOS pass transistor P_(i) ofthe i^(th) first control circuit C_(i) As a result, the boosted voltageat the first terminal of the boost capacitor 23 is applied to the i^(th)output O_(i), as an output voltage V_(boostni). The dischargingtransistor N_(i) of the i^(th) first control circuit C_(i) is open,since its gate is controlled by SRi which is “low”.

In the case of a shift register with non-overlapping outputs, only oneof the output signals SRi is “high” at any one time. In this case, whenthe i^(th) output SRi from the shift register is “high”, the otheroutputs O_(j), where j=0, 1 . . . (m−1) except for j=i, are isolatedfrom the first-terminal of the boost capacitor 23, so that the boostedvoltage is applied only to the i^(th) output O_(i). In the embodiment ofFIG. 21 this is achieved since in the j^(th) second control circuit,where i≠j, the gate of the second pass switch T_(j) is connected to thefirst terminal of the boost capacitor 23. So the second pass switchT_(j) is only closed when SRmux is “low”, i.e. when all shift registeroutputs are “low”. During this time, the boosted voltage at the secondterminal 53 of the additional capacitor 29 is applied to the gate of thefirst pass switch P_(j) in the j^(th) first control circuit C_(j). WhenSRmux is “high” (i.e. when any shift register output is “high”), thesecond pass switch T_(j) is open and the gate of the first pass switchP_(j) in the j^(th) first control circuit C_(j) is floating. However,the boosted voltage previously on the gate of the first pass switchP_(j) in the j^(th) first control circuit C_(j) is maintained by beingstored in the parasitic capacitances of the gate of first pass switchP_(j), and the first pass switch P_(j) remains open. At the same time,the discharging transistor N_(j) in the j^(th) first control circuit isturned on since its gate is controlled by SRj which is high, so that thelower supply voltage V_(SS) is applied to the j^(th) output O_(j).

The outputs SRi of the shift register are arranged to be “high” insequence, and such that only one of the output signals is “high” at anyone time. The upper part of the circuit of FIG. 21 will deliver anoutput voltage greater than the higher supply voltage V_(DD) to each ofthe output terminals in sequence. For example, the shift registeroutputs are typically arranged such that SR0 is initially high, followedby SR1 high, followed by SR2 high, and so on in sequence, in which casea boosted output voltage will initially be provided to the outputterminal O₀, then to the output terminal 0 ₁, then to the outputterminal 0 ₂ and so on.

In the circuit of FIG. 21, it is necessary to turn off the passtransistor P_(i) of the i^(th) first control circuit C_(i) when thei^(th) output from the shift register goes “low”. However, the firstterminal of the boost capacitor 12 will still be at a boosted voltagewhile another output from the shift register is “high” so that SRmuxremains “high”. As a result in the circuit of FIG. 21, in which the passtransistor P_(i) of the i^(th) first control circuit C_(i) is embodiedas a PMOS device, it is necessary to apply a voltage greater thanV_(boost23)−V_(pT) to the gate of the pass transistor P_(i) of thei^(th) first control circuit C_(i) in order to turn it off (whereV_(boost23) is the potential at the first terminal 23 of the boostcapacitor and V_(pT) is the threshold of the p-type pass transistorP_(i)). In the embodiment of FIG. 21, a sufficiently large gate voltageto turn off the pass transistor P_(i) of the i^(th) first controlcircuit C_(i) is obtained by deriving the gate voltage from the upperterminal 53 of the additional capacitor 29 via the second pass switchT_(i) of the i^(th) second control circuit K_(i).

The lower half of the voltage boost circuit of FIG. 21 is complementaryto the upper half. One of the outputs O′_(i) will provide an outputvoltage V_(BOOSTp) which is lower than the lower supply voltage V_(SS),with all other outputs providing an output of the higher supply voltageV_(DD).

The voltage boost circuits of FIGS. 11, 12, 17, 19, 20 and 21 canprovide both a voltage boosted above the higher supply voltage V_(DD)(for driving n-type sampling switches) and a voltage boosted below thelower supply voltage V_(SS) (for driving p-type sampling switches). Inapplications where it is necessary to drive only n-type samplingswitches or to drive only p-type sampling switches, a voltage boostcircuit of one of these embodiments may consist of only the upperportion or of only the lower portion.

The present invention has been described with reference to itsapplication as a source driver circuit. However, a drive circuit of theinvention is not limited to use as a source driver circuit but has otherpossible applications. For example, a drive circuit of the invention maybe used in any application where it is desired to sample analoguereferences in a data converter.

As an example, FIG. 22 illustrates a drive circuit according to afurther embodiment of the invention. This embodiment relates to aswitched capacitor digital/analogue converter (DAC) for converting ann-bit digital word to a corresponding analogue output. The DAC comprisesn capacitors F₁, . . . , F_(n) and further comprises a terminatingcapacitor F_(TERM). The first electrodes of the capacitors F₁, . . . ,F_(n) are connected together and to the first terminal of theterminating capacitor F_(TERM). The second terminal of each of thecapacitors F₁, . . . , F_(n) is connected to a respective switch, suchas switch 60, which selectively connects the second electrode to a firstor second reference voltage input V₁ or V₂ in accordance with the stateor value of a corresponding bit of the digital word. The output of theDAC drives a load (not shown), for example in the form of a data line orcolumn electrode of an active matrix of a liquid crystal device.

The DAC has two phases of operation, namely a resetting or “zeroing”phase and a converting or “decoding” phase, controlled by internallygenerated timing signals which are not illustrated in FIG. 22. Duringthe zeroing phase, the first and second electrodes of the capacitors F₁,. . . , F_(n) and the first electrode of the terminating capacitorF_(TERM) are connected together by an electronic switch 61 and to thefirst reference voltage input V₁. The capacitors F₁, . . . , F_(n) aretherefore discharged so that the total charge stored in the DAC is equalto V₁F_(TERM).

During the decoding phase, the second electrode of each capacitor F_(i)is connected to the first reference voltage input V₁ or to the secondreference voltage input V₂ according to the value of the i^(th) bit ofthe digital input word.

The electronic switch 61 is controlled by a clock signal that isgenerated by a clock logic block 62. The clock logic block is connectedbetween a first power supply rail that provides a first supply voltageV_(dd) and a second power supply rail that provides a second voltageV_(ss) where V_(dd)>V_(ss). The clock signal thus varies between avoltage level V_(dd) and a voltage level V_(ss).

During the zeroing phase the electronic switch 61 connects the upperplate of each capacitor to the first reference voltage V₁. Theelectronic switch has to charge all the capacitors quickly, and therequirements on the electronic switch 61 are therefore similar to therequirements for the sampling gates described above. It is thereforenormal for the electronic switch 61 to have a large area, and/or tooperate on voltage supply rails that provide a voltage greater than thefirst supply voltage V_(dd) and a voltage lower than the second supplyvoltage V_(ss). As in the case of the shift register described above,this is unsatisfactory. Making the electronic switch 61 large presents alarge parasitic capacitance to the DAC and affects its operation,whereas operating the electronic switch 61 at a high voltage consumesmore power and requires the provision of additional voltage supplyrails.

According to the embodiment of FIG. 22, therefore, the clock signal fromthe clock logic block is boosted by a voltage boost circuit 63 thatincreases the level of the clock signal so that the clock signalsupplied to the electronic switch 61 varies between a voltage levelV_(ddh) and a voltage level V_(ssh), whereV_(ddh)>V_(dd)>V_(ss)>V_(ssh). The voltage boost circuit 63 uses thesame voltage supply rails as the clock logic block 61 (i.e., the firstpower supply rail V_(dd) and the second power supply rail V_(ss)), sothat power consumption is reduced and the need to provide additionalvoltage supply rails is eliminated.

The electronic switch 61 may be either a single channel switch or acomplementary switch, as described above.

FIG. 23 shows a further voltage boost circuit suitable for use in adrive circuit of the present invention. As described for the voltageboost circuit of FIG. 12, the voltage boost circuit of FIG. 23 can, whenthe output SRi of the shift register is “low”, provide a voltage at theV_(boostn) output 17 that is lower than the lower supply voltage V_(SS)(in addition to, when the output SRi of the shift register is “high”,providing a voltage at the V_(boostn) output 17 that is higher than thehigher supply voltage V_(DD)). Conversely, the voltage boost circuit ofFIG. 23 can provide at the V_(boostp) output 17′ a voltage that is lowerthan the lower supply voltage V_(SS) (when the output SRi of the shiftregister is “high”) and a voltage that is higher than the higher supplyvoltage V_(DD) (when the output SRi of the shift register is “low”)

Providing an output voltage at the V_(boostn) output 17 that is lowerthan the lower supply voltage V_(SS) when the output SRi of the shiftregister is “low” ensures that, when the output voltage is used tocontrol n-type TFT sampling switches, the n-type TFT sampling switchesare OFF in applications in which the sampled voltages exceed the supplyvoltages during periods of no sampling (i.e., when the output SRi of theshift register is “low”). Conversely, providing an output voltage at theV_(boostp) output 17′ that is higher than the higher supply voltageV_(DD) when the output SRi of the shift register is “low” ensures that,when the output voltage is used to control p-type TFT sampling switches,the p-type TFT sampling switches are OFF during periods of no sampling.

The voltage boost circuit of FIG. 23 is a more efficient implementationof the voltage boost circuit of FIG. 12, particularly in applicationsthat require both V_(BOOSTn) and V_(BOOSTp). As can be seen, thetransistors 30,30′ and the additional capacitors 29,29′ of FIG. 12 havebeen eliminated. A further advantage is that the gates of the switches33 and 33′ in FIG. 23 are driven by the ON voltages of V_(BOOSTp) andV_(BOOSTn) respectively (where the “ON voltage” denotes the voltage atthe output terminals 17,17′ when the output SRi of the shift register is“high”), allowing the capacitors 32 and 32′ to be fully charged.

FIG. 20 above shows the boosted ON voltages being used to chargereservoir capacitors, which are used to generate high voltage supplyrails V_(DDH) and V_(SSH). In the case of a voltage boost circuit whichproduces boosted OFF voltages (where the “OFF voltage” denotes thevoltage at the output terminals 17,17′ when the output SRi of the shiftregister is “low”)—as in the voltage boost circuits of FIG. 12 or23—either the boosted ON voltages or the boosted OFF voltages can beused to charge reservoir capacitors and/or generate high voltage supplyrails V_(DDH) and V_(SSH).

FIG. 24 shows how the boosted OFF voltages generated by the voltageboost circuit of FIG. 23 may be used to generate the boosted voltagesV_(DDH) and V_(SSH). The voltage boost circuit of FIG. 24 corresponds tothe voltage boost circuit of FIG. 23, except that it further comprises aswitch 64 connected at one end to the node 31′ between the transistor33′ and the capacitor 32′, and a switch 64′ connected at one end to thenode 31 between the transistor 33 and the capacitor 32. The switches 64,64′ are arranged to be open when the output SRi of the shift register is“low”—in the embodiment of FIG. 24 the switch 64 is embodied as an PMOStransistor and the switch 64′ is embodied as an NMOS transistor. Thus,when the output SRi of the shift register is “low”, the output voltageat the V_(boostn) output 17 is connected to a “boost output” 65′ via theswitch 28 and the additional switch 64′—so that the voltage lower thanthe lower supply voltage V_(SS) generated at the V_(boostn) output 17 ispassed to the boost output 65′. Similarly, when the output SRi of theshift register is “low”, the output voltage at the V_(boostp) output 17′is connected to another “boost output” 65 via the switch 28′ and theadditional switch 64—so that the voltage higher than the higher supplyvoltage V_(DD) generated at the V_(boostp) output 17′ is passed to theboost output 65.

It would in principle be possible to combine the embodiments of FIGS. 20and 24 and provide a voltage boost circuit having the switches 48,48′ ofFIG. 20 and the switches 64,64′ of FIG. 24. Such a voltage boost circuitcould provide V_(DDH)/V_(SSH) outputs for both high and low values ofthe shift register output.

INDUSTRIAL APPLICABILITY

A drive circuit of the invention may be integrated on a substrate of anAMLCD that uses thin film transistors (TFTs). A circuit of the inventionmay be of particular advantage when applied in displays for mobileapplications or in other situation where it is desirable for powerconsumption and system complexity to be kept to a minimum.

1. A drive circuit comprising: a logic block connected between a sourceof a first voltage and a source of a second voltage, the first voltagebeing greater than the second voltage; and at least one samplingcircuit, the or each sampling circuit for sampling an analogue input andoutputting a voltage to a respective output; wherein the logic blockoutputs, in use, a respective output signal for each sampling circuit;wherein the drive circuit further comprises at least one voltage boostcircuit, the or each voltage boost circuit being associated with arespective one of the sampling circuits and, upon receiving therespective signal output from the logic block, generating a boostedvoltage signal and providing the boosted voltage signal to therespective sampling circuit; and wherein each voltage boost circuit isconnected between the source of the first voltage and the source of thesecond voltage.
 2. A drive circuit as claimed in claim 1 wherein eachvoltage boost circuit comprises a boost capacitor having a firstterminal connectable to the input to a respective sampling circuit; acharging circuit for charging, in a charging period, the boost capacitorto substantially one of the first and second voltages; and a boostcircuit for, in a boosting period, connecting a second terminal of theboost capacitor to a boost bias voltage.
 3. A drive circuit as claimedin claim 2 wherein the boost bias voltage is one of the first and secondvoltages.
 4. A drive circuit as claimed in claim 2 wherein the chargingcircuit comprises a first switch connected between the source of thefirst or second voltage and the first terminal of the boost capacitor.5. A drive circuit as claimed in claim 2 wherein the boost circuitcomprises a second switch connected between the source of the first orsecond voltage and the second terminal of the boost capacitor.
 6. Adrive circuit as claimed in claim 2, wherein the boost circuit comprisesa second switch having a first terminal connected to the source of thefirst or second voltage, the second switch being controlled by thepotential at the first terminal of the boost capacitor; and wherein thefirst switch is controlled by the potential at the second terminal ofthe second switch.
 7. A drive circuit as claimed in claim 2, wherein theboost bias voltage is a respective output signal from the logic block.8. A drive circuit as claimed in claim 2 wherein each voltage boostcircuit comprises a pass switch for disconnecting the first terminal ofthe boost capacitor from an output of the voltage boost circuit duringthe charging period.
 9. A drive circuit as claimed in claim 7 whereineach voltage boost circuit further comprises a discharging switch forconnecting the output of the voltage boost circuit to the other of thefirst and second voltages, the discharging switch being controlled to beopen when the pass switch is closed.
 10. A drive circuit as claimed inclaim 4 wherein the first switch is a transistor.
 11. A drive circuit asclaimed in claim 10 wherein the first switch is a diode-connectedtransistor.
 12. A drive circuit as claimed in claim 10 wherein the firstswitch is controlled by a respective output signal from the logic block.13. A drive circuit as claimed in claim 8 wherein the logic block is ashift register.
 14. A drive circuit as claimed in claim 13 wherein eachvoltage boost circuit comprises a second pass switch for connecting thefirst terminal of the boost capacitor to the output of the voltage boostcircuit during at least part of the charging period.
 15. A drive circuitas claimed in claim 13 wherein the output of a voltage boost circuit isconnectable to the output of the voltage boost circuit for a precedingsource line.
 16. A drive circuit as claimed in claim 2 and furthercomprising a switch for connecting the first terminal of the boostcapacitor to a storage capacitor during the boost phase.
 17. A drivecircuit as claimed in claim 2 wherein the voltage boost circuits share acommon boost capacitor.
 18. A drive circuit as claimed in claim 1,wherein each voltage boost circuit generates a boosted voltage signalhaving a voltage greater than the first voltage.
 19. A drive circuit asclaimed in any of claims 1, wherein each voltage boost circuit generatesa boosted voltage signal having a voltage lower than the second voltage.20. A drive circuit as claimed in any of claims 1, wherein each voltageboost circuit generates, at a first output, a first boosted voltagesignal having a voltage greater than the first voltage and generates, ata second output, a second boosted voltage signal having a voltage lowerthan the second voltage.
 21. A display device comprising a drive circuitas defined in claim
 1. 22. A display device comprising a drive circuitas defined in claim
 2. 23. A display device as claimed in claim 22wherein the drive circuit further comprises a switch for connecting thefirst terminal of the boost capacitor to a storage capacitor during theboost phase.
 24. A display device as claimed in claim 22 wherein thevoltage boost circuits share a common boost capacitor.
 25. A displaydevice as claimed in claim 22 wherein the voltage boost circuitcomprises a second switch having a first terminal connected to thesource of the first or second voltage, the second switch beingcontrolled by the potential at the first terminal of the boostcapacitor; and wherein the first switch is controlled by the potentialat the second terminal of the second switch.
 26. A display device asclaimed in claim 21 wherein each voltage boost circuit generates aboosted voltage signal having a voltage greater than the first voltage.27. A display device as claimed in claim 21 wherein each voltage boostcircuit generates a boosted voltage signal having a voltage lower thanthe second voltage.
 28. A display device as claimed in claim 21 whereineach voltage boost circuit generates, at a first output, a first boostedvoltage signal having a voltage greater than the first voltage andgenerates, at a second output, a second boosted voltage signal having avoltage lower than the second voltage.
 29. A display device as claimedin claim 21, wherein the display device comprises a plurality of sourcelines, each source line being connected to a respective output of thedrive circuit.
 30. A display device as claimed in claim 21 andcomprising a liquid crystal display device.
 31. A display device asclaimed in claim 30 and comprising an active matrix liquid crystaldisplay device.